Datasheet

MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
12Maxim Integrated
Communications Protocol
The DIO serial interface is used for asynchronous serial
data communications between the device and a host
calibration test system. The device automatically detects
the baud rate of the host computer when the host trans-
mits the initialization sequence. Baud rates between
4800bps and 38,400bps can be detected and used
regardless of the internal oscillator frequency setting.
Data format is always 1 start bit, 8 data bits, 1 stop bit,
and no parity. Communications are only allowed when
the device is in digital mode.
Initialization Sequence
Sending the initialization sequence shown below enables
the device to establish the baud rate that initializes the
serial port. The initialization sequence is 1 byte transmis-
sion of 01hex, as follows: 1111111101000000011111111.
The first start bit 0 initiates the baud-rate synchronization
sequence. The 8 data bits 01hex (LSB first) follow this
and then the stop bit, which is indicated above as a
1, terminates the baud-rate synchronization sequence.
This initialization sequence on OUT/DIO should occur
after a period of 2ms after stable power is applied to the
device. This allows time for the power-on-reset function
to complete.
Serial-Interface Command Format
All communication commands into the device follow a
defined format utilizing an interface register set (IRS).
The IRS is an 8-bit command that contains both an
interface register set data (IRSD) nibble (4 bits) and an
interface register set address (IRSA) nibble (4 bits). All
internal calibration registers and flash memory locations
are accessed for read and write through this interface
register set. The IRS byte command is structured as
follows:
IRS[7:0] = IRSD[3:0], IRSA[3:0]
where:
IRSA[3:0] is the 4-bit interface register set address
and indicates which register receives the data nibble
IRSD[3:0];
IRSA[0] is the first bit on the serial interface after the
start bit;
IRSD[3:0] is the 4-bit interface register set data;
IRSD[0] is the 5th bit received on the serial interface
after the start bit
The IRSA address decoding is shown in Table 14.
Special Command Sequences
A special command register to internal logic (CRIL[3:0])
causes execution of special command sequences within
the device. These command sequences are listed as
CRIL command codes, as shown in Table 15.
Write Examples
A 16-bit write to any of the internal calibration registers is
performed as follows:
1) Write the 16 data bits to DHR[15:0] using 4 byte
accesses into the interface register set.
2) Write the address of the target internal calibration
register to ICRA[3:0].
3) Write the load internal calibration register (LdICR)
command to CRIL[3:0]. When a LdICR command is
issued to the CRIL register, the calibration register
loaded depends on the address in the internal cali-
bration register address (ICRA). Table 16 specifies
which calibration register is decoded.
Figure 2. OUT/DIO Output Data Format
DRIVEN BY TESTER DRIVEN BY MAX1454
THREE-STATE
NEED WEAK
PULLUP*
THREE-STATE
NEED WEAK
PULLUP*
START-BIT
LSB
START-BIT
LSB
MSB
STOP-BIT
MSB
STOP-BIT
111110100110 1
0
1111 1111 000001000111111111
OUT/DIO
*PROGRMMABLE DELAY DETERMINED BY READDLY SETTING.