Datasheet

MAX1415/MAX1416
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX1415 (continued)
(V
DD
= 3V, GND = 0, V
REF+
= 1.225V, V
REF-
= GND, external f
CLKIN
= 2.4576MHz, CLKDIV bit = 0, C
REF+
to GND = 0.1µF, C
REF-
to
GND = 0.1µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DOUT and DRDY, I
SOURCE
= 100µA
V
DD
-
0.6V
Output-Voltage High V
OH
CLKOUT, I
SOURCE
= 10µA
V
DD
-
0.6V
V
Tri-State Leakage Current I
L
DOUT only ±10 µA
Tri-State Output Capacitance C
OUT
DOUT only 9 pF
SYSTEM CALIBRATION
Full-Scale Calibration Range
GAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 ×
V
REF
/
GAIN
1.05 ×
V
REF
/
GAIN
V
Offset Calibration Range
GAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 ×
V
REF
/
GAIN
1.05 ×
V
REF
/
GAIN
V
Input Span
GAIN = selected PGA gain (1 to 128)
(Notes 10, 11)
0.8 ×
V
REF
/
GAIN
2.1 ×
V
REF
/
GAIN
V
POWER REQUIREMENTS
Power-Supply Voltage V
DD
2.7 3.6 V
Unbuffered, f
CLKIN
= 1MHz, gain = 1 to 128 0.40
Buffered, f
CLKIN
= 1MHz, gain = 1 to 128 0.725
Gain = 1 to 4 0.55
Unbuffered,
f
CLKIN
= 2.4576MHz
Gain = 8 to 128 0.55
Gain = 1 to 4 0.825
Buffered,
f
CLKIN
= 2.4576MHz
Gain = 8 to 128 1.0
mA
Power-Supply Current (Note 12) I
DD
Power-down mode (Note 13) 8 µA
Power-Supply Rejection Ratio PSRR V
DD
= 2.7V to 3.6V (Note 14) dB
EXTERNAL-CLOCK TIMING SPECIFICATIONS
CLKIN Frequency f
CLKIN
(Note 15) 400 2500 kHz
Duty Cycle 40 60 %
INTERNAL-CLOCK TIMING SPECIFICATIONS
MAX1415AE__,
f
CLK
= 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T
A
= -40°C to
+85°C
±4
MAX1415C__,
f
CLK
= 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T
A
= 0°C to
+70°C
±4
T
A
= -40°C to 0°C±7
Internal-Clock Frequency f
CLK
MAX1415E__,
f
CLK
= 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T
A
= 0°C to + 85°C ±4
%