Datasheet
MAX1415/MAX1416
To minimize gain errors in unbuffered mode, select a
source impedance less than the maximum values
shown in Figures 2 and 3. These are the maximum
external resistance/capacitance combinations allowed
before gain errors greater than 1 LSB are introduced in
unbuffered mode.
Enable the internal input buffer for a high source imped-
ance. This isolates the inputs from the sampling capaci-
tor and reduces the sampling-related gain error. When
using the internal buffer, limit the absolute input voltage
range to (V
GND
+ 50mV) to (V
DD
- 1.5V). Properly set
up the gain and common-mode voltage range to mini-
mize linearity errors.
Input Voltage Range
In unbuffered mode, the absolute analog input voltage
range is from (GND - 30mV) to (V
DD
+ 30mV) (see the
Electrical Characteristics section). In buffered mode,
the analog input voltage range is reduced to (GND +
50mV) to (V
DD
- 1.5V). In both buffered and unbuffered
modes, the differential analog input range (V
AIN+
- V
AIN-
)
decreases at higher gains (see the Programmable Gain
Amplifier and Unipolar and Bipolar Modes sections).
Reference
The MAX1415/MAX1416 provide differential inputs,
REF+ and REF-, for an external reference voltage.
Connect the external reference directly across REF+ and
REF- to obtain the differential reference voltage, V
REF
.
The common-mode voltage range for V
REF+
and V
REF-
is between GND and V
DD
. For specified operation, the
nominal voltage, V
REF
is 1.225V for the MAX1415 and
2.5V for the MAX1416.
The MAX1415/MAX1416 sample REF+ and REF- at
f
CLKIN
/64 (CLKDIV = 0) or f
CLKIN
/128 (CLKDIV = 1)
with an internal 10pF (typ for gain = 1) sampling capac-
itor in series with a 7kΩ (typ) switch on-resistance.
Programmable Gain Amplifier
A PGA provides selectable levels of gain: 1, 2, 4, 8, 16,
32, 64, and 128. Bits G0, G1, and G2 in the setup reg-
ister control the gain (see Table 9). As the gain increas-
es, the value of the input sampling capacitor, C
SAMP
,
also increases (see Table 5). The dynamic load pre-
sented to the analog inputs increases with clock fre-
quency and gain in unbuffered mode (see the Input
Buffers section and Figure 1).
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
20 ______________________________________________________________________________________
HIGH-
IMPEDANCE
INPUT
R
SW
(7kΩ TYP)
C
TOTAL
(7pF TYP FOR GAIN = 1)
AIN(+)
AIN(-)
V
BIAS
C
TOTAL
= C
SAMP
+ C
STRAY
Figure 1. Unbuffered Analog Input Structure
MAXIMUM EXTERNAL RESISTANCE
vs. MAXIMUM EXTERNAL CAPACITANCE (1MHz)
0.1
1
10
100
1 10 100 1000 10,000
EXTERNAL CAPACITANCE (pF)
EXTERNAL RESISTANCE (kΩ)
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8 TO 128
Figure 2. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (1MHz)
MAXIMUM EXTERNAL RESISTANCE
vs. MAXIMUM EXTERNAL CAPACITANCE
(2.4576MHz)
0.1
1
10
100
1 10 100 1000 10,000
EXTERNAL CAPACITANCE (pF)
EXTERNAL RESISTANCE (kΩ)
GAIN = 2
GAIN = 4
GAIN = 8 TO 128
GAIN = 1
Figure 3. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (2.4576MHz)