Datasheet

MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
_______________________________________________________________________________________ 7
Note 1: Single conversion.
Note 2: DNL and INL are measured between code 010hex and 3FFhex.
Note 3: Offset error is referenced to code 010hex.
Note 4: Output swing is a function of external gain-setting feedback resistors and REF voltage.
Note 5: Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DV
DD
.
Note 6: SHDN stays high if the PLL is on.
Note 7: Actual worst-case performance is ±2.5LSB. Guaranteed limit of ±3.5LSB is due to production test limitation.
Note 8: Guaranteed by design. Not production tested.
TIMING CHARACTERISTICS (continued)
(MAX1407/MAX1408/MAX1409/MAX1414: AV
DD
= DV
DD
= 2.7V to 3.6V, T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TYPICAL TIMING PARAMETERS
OUT1/OUT2 Turn-Off Time
Input impedance > 1MΩ
(MAX1407/MAX1409/MAX1414 only)
100 µs
Sleep Voltage Monitor Timeout
Period
t
DSLP
The delay for the sleep voltage monitor
output, RESET, to go high after AV
DD
rises
above the reset threshold (+1.8V when bit
VM = 1 and +2.7V, when bit VM = 0); this is
largely driven by the startup of the 32kHz
oscillator
1.54 s
WU1 or WU2 Pulse Width t
WU
Minimum pulse width required to detect a
wake-up event
1µs
Shutdown Deassert Delay t
DPU
The delay for SHDN to go high after a valid
wake-up event
1µs
FOUT Turn-On Time t
DFON
The turn-on time for the high-frequency
clock; it is gated by an AND function with
three signals—the RESET signal, the internal
low voltage V
DD
monitor signal, and the
assertion of the PLL; the time delay is timed
from when the low-voltage monitor trips or
the RESET going high, whichever happens
later; FOUT always starts in the low state
31.25 ms
INT Delay t
DFI
The delay for INT to go low after the FOUT
clock output has been enabled; INT is used
as an interrupt signal to inform the µP the
high-frequency clock has started
7.82 ms
FOUT Disable Delay t
DFOF
The delay after a shutdown command has
asserted and before FOUT is disabled; this
gives the microcontroller time to clean up
and go into Sleep mode properly
1.95 ms
SHDN Assertion Delay t
DPD
The delay after a shutdown command has
asserted and before SHDN is pulled low
(turning off the DC-DC converter) (Note 6)
2.93 ms