Datasheet

RS-485 Transceivers with Low-Voltage
Logic Interface
Test Circuits and Waveforms
Y
Z
V
OD
V
OC
R
L
/2
R
L
/2
Figure 1. Driver DC Test Load
DI
V
L
0
Z
Y
V
O
0
-V
O
V
O
V
L
/2
t
DPLH
t
DPHL
1/2 V
O
10%
t
R
90%
90%
1/2 V
O
10%
t
F
V
DIFF
= V (Y) - V (Z)
V
DIFF
t
SKEW
=
|
t
DPLH
-
t
DPHL
|
Figure 3. Driver Propagation Delays
DI
DE
V
L
D
Z
Y
V
OD
R
L
C
L
Figure 2. Driver Timing Test Circuit
MAX13430E–MAX13433E
8
Maxim Integrated