Datasheet

MAX13335E/MAX13336E
Dual Automotive Differential Audio Receivers
with I
2
C Control and Diagnostics
13
Acknowledge Bit
The acknowledge bit (ACK) is a clocked 9th bit that the
device uses to handshake the receipt of each byte of
data when in write mode. The device pulls down SDA
during the entire master-generated 9th clock pulse if
the previous byte is successfully received (Figure 5).
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master could retry communication. The mas-
ter must pull down SDA during the 9th clock cycle to
acknowledge receipt of data when the device is in read
mode. An acknowledge must be sent by the master
after each read byte to allow data transfer to continue.
A not-acknowledge is sent when the master reads the
final byte of data from the device, followed by a STOP
condition.
Slave Address
The device is programmable to one of the four I
2
C slave
addresses (Table 2). The power-on default I
2
C slave address
of the device for read/write is 0xD0/0xD1 (1101000R/W). The
I
2
C slave address of the device can be selected by writing
to Control Register 1 (0x03) while INT is pulled low externally
during the I
2
C write duration (Figure 6).
Single Byte-Write Operation
For a single byte-write operation, send the slave address
as the first byte followed by the register address and then
a single data byte (Figure 7).
Figure 5. Acknowledge and Not-Acknowledge Bits
Figure 6. I
2
C Slave Address Programming
Figure 7. A Single Byte-Write Operation
SDA
S
SCL
18
NOT ACKNOWLEDGE
ACKNOWLEDGE
9
SDA 11 11100 00000
CONTROL REGISTER 1 (0x03) PROGRAM I
2
C ADDRESSCURRENT I
2
C ADDRESS
00000000 ACK ACK ACKI2C1 I2C1I2C0 I2C0
SCL
INT
S S7 S6 S5 S4 S3 S2 S1 ACK
B7 B6 B5 B4 B3 B2 B1 B0 ACK P
C7 C6 C5 C4 C3 C2 C1 C0 ACK
R/W
= 0
SLAVE ADDRESS
DATA 1
REGISTER ADDRESS