Datasheet

Start Bit
Communication with the MAX1300/MAX1301 is accom-
plished using the three input data word formats shown in
Table 3. Each input data word begins with a start bit. The
start bit is defined as the first high bit clocked into DIN with
CS low when any of the following are true:
• Data conversion is not in process and all data from the
previous conversion has clocked out of DOUT.
• The device is configured for operation in external clock
mode (mode 0) and previous conversion-result bits
B15–B3 have clocked out of DOUT.
• The device is configured for operation in external
acquisition mode (mode 1) and previous conversion-
result bits B15–B7 have clocked out of DOUT.
• The device is configured for operation in internal clock
mode, (mode 2) and previous conversionresult bits
B15–B4 have clocked out of DOUT.
Output Data Format
Output data is clocked out of DOUT in offset binary format
on the falling edge of SCLK, MSB first (B15). For output
binary codes, see the Transfer Function section and
Figures 12, 13, and 14.
Conguring Analog Inputs
Each analog input has two configurable parameters:
• Single-ended or true-differential input
• Input voltage range
These parameters are configured using the analog input
configuration byte as shown in Table 2. Each analog input
has a dedicated register to store its input configuration
information. The timing diagram of Figure 15 shows how
to write to the analog input configuration registers. Figure
16 shows DOUT and SSTRB timing.
Transfer Function
An ADC’s transfer function defines the relationship
between the analog input voltage and the digital out-
put code. Figures 12, 13, and 14 show the MAX1300/
MAX1301 transfer functions. The transfer function is
determined by the following characteristics:
• Analog input voltage range
• Single-ended or differential configuration
• Reference voltage
The axes of an ADC transfer function are typically in least
significant bits (LSBs). For the MAX1300/MAX1301, an
LSB is calculated using the following equation:
REF
N
FSR V
1 L S B
2 4.096V
×
=
×
where N is the number of bits (N = 16) and FSR is the
full-scale range (see Figures 7 and 8).
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 3 x V
REF
)
Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 12 x V
REF
)
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 6 x V
REF
)
INPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
1260-6-12
-12
-8
-4
0
4
8
12
-16
-18 18
INPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
1260-6-12
-12
-8
-4
0
4
8
12
-16
-18 18
INPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
1260-6-12
-12
-8
-4
0
4
8
12
-16
-18 18
MAX1300/MAX1301 8- and 4-Channel, ±3 x V
REF
Multirange Inputs,
Serial 16-Bit ADCs
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