Datasheet

Figure 4. Internal Clock-Mode Conversion (Mode 2)
Figure 5. Analog Input Current vs. Input Voltage Figure 6. Simplified Analog Input Circuit
CS
SCLK
1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24
DIN
S C2 C1 C0 0 0 0 0
ANALOG INPUT
TRACK AND HOLD*
TRACK
DOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
BYTE 1
BYTE 2 BYTE 3
SSTRB
INTCLK**
1 2 3 25 26 27 28
9 10
11
12 13 14 15 16
10 11 12 13 14
HOLD HOLD
t
ACQ
100ns to 400ns
f
INTCLK
4.5MHz
f
SAMPLE
f
SCLK
/ 24 + f
INTCLK
/ 28
*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
HIGH IMPEDANCE
ANALOG INPUT VOLTAGE (V)
ANALOG INPUT CURRENT (mA)
0
-0.6
-0.2
0.2
0.6
1.0
-1.0
ALL MODES
(+3 x V
REF
)/2
(-3 x V
REF
)/2
-3 x V
REF
+3 x V
REF
MAX1300
MAX1301
R2
R1
V
SJ
*R
SOURCE
ANALOG
SIGNAL
SOURCE
R2
R1
V
SJ
*R
SOURCE
ANALOG
SIGNAL
SOURCE
IN_+
IN_+
*MINIMIZE R
SOURCE
TO AVOID GAIN ERROR AND DISTORTION.
MAX1300/MAX1301 8- and 4-Channel, ±3 x V
REF
Multirange Inputs,
Serial 16-Bit ADCs
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