Datasheet
Figure 8 illustrates the software-selectable differential
analog input voltage range that produces a valid digital
output. Each analog input differential pair can be inde-
pendently programmed to one of three differential input
ranges by setting the R[2:0] control bits with DIF/SGL = 1.
Regardless of the specified input voltage range and
whether the channel is selected, each analog input is
±16.5V fault tolerant. The analog input fault protection is
active whether the device is unpowered or powered. Any
voltage beyond FSR, but within the ±16.5V fault tolerant
range, applied to an analog input results in a full-scale
output voltage for that channel.
Clamping diodes with breakdown thresholds in excess of
16.5V protect the MAX1300/MAX1301 analog inputs dur-
ing ESD and other transient events (Figure 6). The clamp-
ing diodes do not conduct during normal device opera-
tion, nor do they limit the current during such transients.
When operating in an environment with the potential for
high-energy voltage and/or current transients, protect the
MAX1300/MAX1301 externally.
Figure 3. External Acquisition-Mode Conversion (Mode 1)
CS
SCLK
1
2
3
4 5
6
7
8
9
10 11
12
13
14
15
16 17 18 19 20 21 22 23 24 25 26 27
28 29
30 31 32
DIN
S C2 C1 C0 0 0 0 0
ANALOG INPUT
TRACK AND HOLD*
HOLD
DOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
BYTE 1 BYTE 2 BYTE 3 BYTE 4
SSTRB
INTCLK**
1
2
3 14 15
16
17
TRACK HOLD
t
ACQ
100ns to 400ns
f
INTCLK
4.5MHz
f
SAMPLE
f
SCLK
/ 32 + f
INTCLK
/ 17
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
HIGH IMPEDANCE
MAX1300/MAX1301 8- and 4-Channel, ±3 x V
REF
Multirange Inputs,
Serial 16-Bit ADCs
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