Datasheet

Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±3 x V
REF
differential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±3 x V
REF
range
(1010 1100). To initiate a conversion for the CH2 and CH3
differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1300/MAX1301 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD and
-SFDR vs. Input Frequency plot in the Typical Operating
Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-ended
analog input voltage range that produces a valid digital
output. Each analog input channel can be independently
programmed to one of seven single-ended input ranges
by setting the R[2:0] control bits with DIF/SGL = 0.
Figure 2. External Clock-Mode Conversion (Mode 0)
HIGH
IMPEDANCE
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DIN
S C2 C1 C0 0 0 0 0
ANALOG INPUT
TRACK AND HOLD*
DOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
BYTE 1
BYTE 2 BYTE 3 BYTE 4
SSTRB
HOLD TRACK HOLD
t
ACQ
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
f
SAMPLE
f
SCLK
/ 32
SAMPLING INSTANT
MAX1300/MAX1301 8- and 4-Channel, ±3 x V
REF
Multirange Inputs,
Serial 16-Bit ADCs
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