Datasheet

Power Supplies
To maintain a low-noise environment, the MAX1300
and MAX1301 provide separate power supplies for
each section of circuitry. Table 1 shows the four sepa-
rate power supplies. Achieve optimal performance using
separate AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD togeth-
er as close to the device as possible for a convenient
power connection. Connect AGND1, AGND2, AGND3,
DGND, and DGNDO together as close to the device
as possible. Bypass each supply to the corresponding
ground using a 0.1μF capacitor (Table 1). If significant
low-frequency noise is present, add a 10μF capacitor in
parallel with the 0.1μF bypass capacitor.
Converter Operation
The MAX1300/MAX1301 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conversion
technique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both singleended and
differential configurations are supported with program-
mable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1300/MAX1301 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for each
operating mode. The MAX1300/MAX1301 analog input
circuitry buffers the input signal from the sampling capaci-
tors, resulting in a constant input impedance with varying
input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2). The
analog input signal source must be capable of driving the
ADC’s 17kΩ input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The ana-
log inputs are ±16.5V fault tolerant and are protected by
back-to-back diodes. The summing junction voltage, V
SJ
,
is a function of the channel’s input commonmode voltage:
SJ CM
R1 R1
V 2.375V 1 V
R1 R 2 R 1 R 2

 
= × ++ ×

 
++
 

As a result, the analog input impedance is relatively con-
stant over input voltage as shown in Figure 5.
Table 1. MAX1300/MAX1301 Power Supplies and Bypassing
Table 2. Analog Input Configuration Byte
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION BYPASSING
DVDDO/DGNDO 2.7 to 5.25 0.03 Digital I/O 0.1µF to DGNDO
AVDD2/AGND2 4.75 to 5.25 135 Analog Circuitry 0.1µF to AGND2
AVDD1/AGND1 4.75 to 5.25 3.0 Analog Circuitry 0.1µF to AGND1
DVDD/DGND 4.75 to 5.25 0.8 Digital Control Logic and Memory 0.1µF to DGND
BIT
NUMBER
NAME DESCRIPTION
7 START
Start Bit. The rst logic 1 after CS goes low denes the beginning of the analog input conguration byte.
6 C2
Channel-Select Bits. SEL[2:0] select the analog input channel to be congured (Tables 4 and 5).5 C1
4 C0
3
DIF/SGL
Differential or Single-Ended Conguration Bit. DIF/SGL = 0 congures the selected analog input channel
for single-ended operation. DIF/SGL = 1 congures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
2 R2
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.1 R1
0 R0
MAX1300/MAX1301 8- and 4-Channel, ±3 x V
REF
Multirange Inputs,
Serial 16-Bit ADCs
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