Datasheet

The MAX127/MAX128 ignore acknowledge and not-
acknowledge conditions issued by the master during the
read cycle. The device waits for the master to read the
output data or waits until a STOP condition is issued.
Figure 10 shows a complete read cycle.
In unipolar input mode, the output is straight binary. For
bipolar input mode, the output is two’s complement. For
output binary codes see the Transfer Function section.
Applications Information
Power-On Reset
The MAX127/MAX128 power up in normal operating
mode, waiting for a START condition followed by the
appropriate slave address. The contents of the input and
output data registers are cleared at power-up.
Internal or External Reference
The MAX127/MAX128 operate with either an internal or
an external reference (Figures 11a–11c). An external ref-
erence is connected to either REF or to REFADJ.
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at REF from a 2.5V reference.
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.096V at REF.
Bypass REF with a 4.7μF capacitor to AGND and bypass
REFADJ with a 0.01μF capacitor to AGND (Figure 11a).
The internal reference voltage is adjustable to ±1.5% (±65
LSBs) with the reference-adjust circuit of Figure 12.
External Reference
To use the REF input directly, disable the internal buffer
by connecting REFADJ to V
DD
(Figure 11b). Using the
REFADJ input eliminates the need to buffer the reference
externally. When the reference is applied at REFADJ,
bypass REFADJ with a 0.01μF capacitor to AGND
(Figure 11c).
At REF and REFADJ, the input impedance is a minimum
of 10kΩ for DC currents. During conversions, an external
reference at REF must be able to drive a 400μA DC load,
and must have an output impedance of 10Ω or less. If the
reference has higher input impedance or is noisy, bypass
REF with a 4.7μF capacitor to AGND as close to the chip
as possible.
With an external reference voltage of less than 4.096V at
REF or less than 2.5V at REFADJ, the increase in RMS
noise to the LSB value (full-scale voltage/4096) results in
performance degradation and loss of effective bits.
Power-Down Mode
To save power, put the converter into low-current shut-
down mode between conversions. Two programmable
power-down modes are available, in addition to the
hardware shutdown. Select STBYPD or FULLPD by pro-
gramming PD0 and PD1 in the input control byte (Table
4). When software power-down is asserted, it becomes
effective only after the end of conversion. In all power-
down modes, the interface remains active and conversion
results may be read. Input overvoltage protection is active
in all power-down modes.
Figure 10. Complete 2-Wire Serial Read Transmission
START
CONDITION
STOP
CONDITION
LSB DATA BYTEMSB DATA BYTE
SLAVE ADDRESS BYTE
MSB MSB
MSB
LSB LSB LSB
0 1
1 2 7 8 9 10 11 17 18 19 22 23 26 27
R
A D11 D4 A D3 D0 A
FILLED WITH
4 ZEROS
MAX127/MAX128 Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
www.maximintegrated.com
Maxim Integrated │ 13