Datasheet

MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
10 ______________________________________________________________________________________
Pin Description
Positive Supply VoltageV
DD2
16
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to V
DD1
.REFADJ9
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance
when CS is high.
SSTRB12
Serial-Data Input. Data is clocked in at SCLK’s rising edge.DIN13
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and
SSTRB are high impedance.
CS
14
Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle
must be 40% to 60%.)
SCLK15
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a 2.500V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to V
DD1
.
REF8
GroundGND10
Serial-Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
DOUT11
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ).SHDN
7
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
COM6
PIN
Positive Supply VoltageV
DD1
1
FUNCTIONNAME
V
DD2
3k
GND
DOUT
C
LOAD
50pF
C
LOAD
50pF
GND
3k
DOUT
a) High-Z to V
OH
and V
OL
to V
OH
b) High-Z to V
OL
and V
OH
to V
OL
V
DD2
3k
GND
DOUT
C
LOAD
70pF
C
LOAD
20pF
GND
3k
DOUT
a) V
OH
to High-Z b) V
OL
to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
Sampling Analog InputsCH0–CH32–5