Datasheet

Detailed Description
Converter Operation
The MAX127/MAX128 multirange, fault-tolerant ADCs use
successive approximation and internal track/hold (T/H) cir-
cuitry to convert an analog signal to a 12-bit digital output.
Figure 1 shows the block diagram for these devices.
Analog-Input Track/Hold
The T/H circuitry enters its tracking/acquisition mode on
the falling edge of the sixth clock in the 8-bit input control
word and enters its hold/conversion mode when the mas-
ter issues a STOP condition. For timing information, see
the Start a Conversion section.
Input Range and Protection
The MAX127/MAX128 have software-selectable input
ranges. Each analog input channel can be independently
programmed to one of four ranges by setting the appro-
priate control bits (RNG, BIP) in the control byte (Table
1). The MAX127 has selectable input ranges extending
to ±10V (±V
REF
x 2.441), while the MAX128 has select-
able input ranges extending to ±V
REF
. Note that when an
external reference is applied at REFADJ, the voltage at
REF is given by V
REF
= 1.638 x V
REFADJ
(2.4 < V
REF
<
4.18). Figure 2 shows the equivalent input circuit.
A resistor network on each analog input provides a
±16.5V fault protection for all channels. This circuit limits
the current going into or out of the pin to less than 1.2mA,
whether or not the channel is on. This provides an added
layer of protection when momentary overvoltages occur at
the selected input channel, and when a negative signal is
applied at the input even though the device may be con-
figured for unipolar mode. Overvoltage protection is active
even if the device is in power-down mode or V
DD
= 0V.
Digital Interface
The MAX127/MAX128 feature a 2-wire serial interface
consisting of the SDA and SCL pins. SDA is the data I/O
and SCL is the serial clock input, controlled by the master
device. A2–A0 are used to program the MAX127/MAX128
to different slave addresses. (The MAX127/MAX128
only work as slaves.) The two bus lines (SDA and SCL)
must be high when the bus is not in use. External pullup
resistors (1kΩ or greater) are required on SDA and SCL
to maintain I
2
C compatibility. Table 1 shows the input
control-byte format.
Figure 1. Block Diagram
Figure 2. Equivalent Input Circuit
CH2
CH1
CH0
SHDN
CH3
CH4
CH5
CH6
CH7
REFADJ
REF
V
DD
AGND
DGND
12-BIT SAR ADC
IN
REF
CLOCK
OUT
T/H
2.5V
REFERENCE
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
A
V
=
1.638
INT
CLOCK
SDA
A2 A1 A0 SCL
SERIAL INTERFACE LOGIC
10kΩ
MAX127
MAX128
5.12kΩ
R2
R1
CH_
S1
S2
S3
S4
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
ON
C
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX127) OR 5.12kΩ (MAX128)
R2 = 8.67kΩ (MAX127) OR ∞ (MAX128)
MAX127/MAX128 Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
www.maximintegrated.com
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