Datasheet

(V
DD
= +5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF; external clock, f
CLK
= 400kHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
(V
DD
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SDA, SCL)
Input High Threshold Voltage V
IH
0.7 x V
DD
V
Input Low Threshold Voltage V
IL
0.3 x V
DD
V
Input Hysteresis V
HYS
0.05 x V
DD
V
Input Leakage Current I
IN
V
IN
= 0V or V
DD
±0.1 ±10 µA
Input Capacitance C
IN
(Note 4) 15 pF
DIGITAL OUTPUTS (SDA)
Output Low Voltage V
OL
I
SINK
= 3mA 0.4
V
I
SINK
= 6mA 0.6
Three-State Output Capacitance C
OUT
(Note 4) 15 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
2-WIRE FAST MODE
SCL Clock Frequency f
SCL
400 kHz
Bus Free Time Between a
STOP and START Condition
t
BUF
1.3 µs
Hold Time (Repeated)
START Condition
t
HD,STA
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated
START Condition
t
SU,STA
0.6 µs
Data Hold Time t
HD,DAT
0 0.9 µs
Data Setup Time t
SU,DAT
100 ns
Rise Time for Both SDA and SCL
Signals (Receiving)
t
R
C
b
= Total capacitance of one bus line in pF
20 +
0.1 x C
b
300 ns
Fall Time for Both SDA and SCL
Signals (Receiving)
t
F
C
b
= Total capacitance of one bus line in pF
20 +
0.1 x C
b
300 ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
t
F
C
b
= Total capacitance of one bus line in pF
20 +
0.1 x Cb
250 ns
Set-Up Time for STOP Condition t
SU,STO
0.6 µs
Capacitive Load for Each
Bus Line
C
b
400 pF
Pulse Width of Spike Suppressed t
SP
0 50 ns
MAX127/MAX128 Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
www.maximintegrated.com
Maxim Integrated │ 5
Electrical Characteristics (continued)
Timing Characteristics