Datasheet

MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
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Pin Description
PIN NAME FUNCTION
1 AIN- Negative Analog Input
2 REF
Reference Voltage Output. Internal 4.096V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.
3 RGND Reference Ground. Connect RGND to GND.
4V
DD
Positive Analog Supply Voltage (+4.75V to +5.25V). Bypass V
DD
with a 0.01µF capacitor and a 10µF
capacitor to GND.
5, 11 N.C. No Connection
6 GND Ground. GND is internally connected to EP.
7V
L
Positive Logic Supply Voltage (1.8V to V
DD
). Bypass V
L
with a 0.01µF capacitor and a 10µF capacitor
to GND.
8 DOUT Serial Data Output. Data is clocked out on the rising edge of SCLK.
9 CNVST
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
10 SCLK Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
12 AIN+ Positive Analog Input
— EP Exposed Paddle. EP is internally connected to GND.
Detailed Description
The MAX1276/MAX1278 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1276/MAX1278.
RGND
AIN +
GND
DOUT
SCLK
CNVST
CONTROL
LOGIC AND
TIMING
AIN -
V
L
V
DD
REF
12-BIT
SAR
ADC
MAX1276
MAX1278
TRACK AND
HOLD
OUTPUT
BUFFER
REF
4.096V
Figure 3. Functional Diagram
C
IN+
R
IN+
R
IN-
C
IN-
V
AZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
ACQUISITION MODE
C
IN+
R
IN+
R
IN-
C
IN-
V
AZ
AIN+
AIN-
CONTROL
LOGIC
CAPACITIVE
DAC
COMP
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit