Datasheet

MAX1276/MAX1278
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ±5%, V
L
= V
DD
, f
SCLK
= 28.8MHz, 50% duty cycle, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DC Leakage Current ±1 µA
Input Capacitance Per input pin 16 pF
Input Current (Average)
Time averaged at maximum throughput rate
75 µA
REFERENCE OUTPUT (REF)
REF Output Voltage Range Static, T
A
= +25°C
4.086 4.096 4.106
V
Voltage Temperature Coefficient ±50
ppm/°C
I
SOURCE
= 0 to 2mA 0.3
Load Regulation
I
SINK
= 0 to 200µA 0.5
mV/mA
Line Regulation V
DD
= 4.75V to 5.25V, static 0.5
mV/V
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low VIL
0.3 x V
L
V
Input Voltage High VIH 0.7 x V
L
V
Input Leakage Current
I
IL
Output high impedance
±0.2 ±10
µA
POWER REQUIREMENTS
Analog Supply Voltage V
DD
4.75 5.25
V
Digital Supply Voltage V
L
1.8
V
DD
V
Static, f
SCLK
= 28.8MHz 8 11
Static, no SCLK 5 7
Analog Supply Current,
Normal Mode
I
DD
Operational, 1.8Msps 10 13
mA
f
SCLK
= 28.8MHz 2
Analog Supply Current,
Partial Power-Down Mode
I
DD
No SCLK 2
mA
f
SCLK
= 28.8MHz 1
Analog Supply Current,
Full Power-Down Mode
I
DD
No SCLK 0.3 1
µA
Operational, full-scale input at 1.8Msps 1 2.5
Static, f
SCLK
= 28.8MHz 0.4 1
Partial/full power-down mode,
f
SCLK
= 28.8MHz
0.2 0.5
mA
Digital Supply Current (Note 8)
Static, no SCLK, all modes 0.1 1 µA
Positive-Supply Rejection PSR V
DD
= 5V ±5%, full-scale input
±0.2 ±3.0
mV
DIGITAL OUTPUT (DOUT)
Output Load Capacitance C
OUT
For stated timing performance 30 pF
Output Voltage Low V
OL
I
SINK
= 5mA, V
L
≥ 1.8V 0.4 V
Output Voltage High V
OH
I
SOURCE
= 1mA, V
L
≤ 1.8V V
L
- 0.5V V
Output Leakage Current I
OL
Output high impedance
±0.2 ±10
µA