Datasheet

MAX1276/MAX1278
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out on
DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK, enabling
the serial interface to be shared by multiple devices. If
CNVST returns high after the 14th, but before the 16th
SCLK rising edge, DOUT remains active so continuous
conversions can be sustained. The highest throughput is
achieved when performing continuous conversions. Figure
10 illustrates a conversion using a typical serial interface.
Connection to
Standard Interfaces
The MAX1276/MAX1278 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1276/
MAX1278 are compatible with all four modes pro-
grammed with the CPHA and CPOL bits in the SPI or
MICROWIRE control register. Conversion begins with a
CNVST falling edge. DOUT goes low, indicating a con-
version is in progress. Two consecutive 1-byte reads
are required to get the full 12 bits from the ADC. DOUT
transitions on SCLK rising edges. DOUT is guaranteed
to be valid t
DOUT
later and remains valid until t
DHOLD
after the following SCLK rising edge. When using CPOL
= 0 and CPHA = 0, or CPOL = 1 and CPHA = 1, the
data is clocked into the µP on the following rising edge.
When using CPOL = 0 and CPHA = 1, or CPOL = 1 and
CPHA = 0, the data is clocked into the µP on the next
falling edge. See Figure 11 for connections and Figures
12 and 13 for timing. See the Timing Characteristics
section to determine the best mode to use.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire the
12 bits of data from the ADC, QSPI allows the minimum
number of clock cycles necessary to clock in the data.
The MAX1276/MAX1278 require 16 clock cycles from the
µP to clock out the 12 bits of data. Figure 14 shows a
transfer using CPOL = 1 and CPHA = 1. The conversion
result contains three zeros, followed by the 12 data bits,
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
12 ______________________________________________________________________________________
OUTPUT CODE
FULL-SCALE
TRANSITION
111...111
12 3
0
FS
FS - 3/2 LSB
FS = V
REF
DIFFERENTIAL INPUT
VOLTAGE (LSB)
1 LSB =
V
REF
4096
111...110
111...101
000...011
000...010
000...001
000...000
ZS = 0
Figure 8. Unipolar Transfer Function (MAX1276 Only)
OUTPUT CODE
FULL-SCALE
TRANSITION
FS0-FS
FS - 3/2 LSB
DIFFERENTIAL INPUT
VOLTAGE (LSB)
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
1 LSB =
V
REF
4096
FS =
V
REF
2
- FS =
-V
REF
2
ZS = 0
Figure 9. Bipolar Transfer Function (MAX1278 Only)