Datasheet

MAX1276/MAX1278
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1276/MAX1278, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIN+. The negative input capacitor is con-
nected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is convert-
ed. The time required for the T/H to acquire an input sig-
nal is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens. The acquisition time,
t
ACQ
, is the minimum time needed for the signal to be
acquired. It is calculated by the following equation:
t
ACQ
≥ 9 × (RS + R
IN
) × 16pF
where R
IN
= 200Ω, and RS is the source impedance of
the input signal.
Note: t
ACQ
is never less than 104ns and any source
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 20MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to V
DD
and GND allow the analog input pins to swing
from GND - 0.3V to V
DD
+ 0.3V without damage. Both
inputs must not exceed V
DD
or be lower than GND for
accurate conversions.
Serial Interface
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1276/MAX1278 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conver-
sion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
10 ______________________________________________________________________________________
DOUT
MODE
SCLK
CNVST
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
ONE 8-BIT TRANSFER
1ST SCLK RISING EDGE
PPD
0 0 0 D11 D10 D9 D8 D7
NORMAL
REF
ENABLED (4.096V)
Figure 6. SPI Interface—Partial Power-Down Mode
Figure 5. Interface-Timing Sequence
t
ACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
CNVST
t
SETUP
DOUT
SCLK
41412 83 16
HIGH IMPEDANCE
D1D4D6 D5D9 D8 D7D11 D10
POWER-MODE SELECTION WINDOW
D0D2D3