Datasheet

MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
6 _______________________________________________________________________________________
Note 1: Accuracy specifications tested at V
DD
= +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: External reference: V
REF
= 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels. V
IN
= ±5V (MAX1270), V
IN
= ±4V (MAX1271).
Note 4: Guaranteed by design, not production tested.
Note 5: Use static external loads during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.
Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).
Note 9: Not production tested. Provided for design guidance only.
TIMING CHARACTERISTICS
(V
DD
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock; f
CLK
=
2.0MHz (MAX127_B); f
CLK
= 1.8MHz (MAX127_A); T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.)
(Figures 2, 5, 7, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIN to SCLK Setup t
DS
100
ns
DIN to SCLK Hold t
DH
0ns
SCLK Fall to Output Data Valid t
DO
20
170
ns
CS Fall to Output Enable t
DV
C
LOAD
= 100pF
120
ns
CS Rise to Output Disable t
TR
C
LOAD
= 100pF
100
ns
CS to SCLK Rise Setup t
CSS
100
ns
CS to SCLK Rise Hold t
CSH
0ns
SCLK Pulse-Width High t
CH
200
ns
SCLK Pulse-Width Low t
CL
200
ns
SCLK Fall to SSTRB t
SSTRB
C
LOAD
= 100pF
200
ns
CS to SSTRB Output Enable t
SDV
C
LOAD
= 100pF, external clock mode only
200
ns
CS to SSTRB Output Disable t
STR
C
LOAD
= 100pF, external clock mode only
200
ns
SSTRB Rise to SCLK Rise t
SCK
Internal clock mode only (Note 4) 0 ns