Datasheet

MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
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Pin Description
D01010
INT
1111
RD
1212
WR
1313
CLK1414
D466
D377
D288
D199
D555
D644
1
D733
D822
D9
1
Tri-State Digital I/O Line (D0)
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read opera-
tion on the data bus.
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock.
In internal clock mode, connect this pin to either V
DD
or GND.
Tri-State Digital I/O Line (D4)
Tri-State Digital I/O Line (D3)
Tri-State Digital I/O Line (D2)
Tri-State Digital I/O Line (D1)
Tri-State Digital I/O Line (D5)
Tri-State Digital I/O Line (D6)
Tri-State Digital I/O Line (D7)
Tri-State Digital Output (D8)
Tri-State Digital Output (D9)
GND1923
REFADJ2024
CH2—19
CH11620
CH01721
COM1822
CH3—18
CH4—17
CH5—16
CS
1515
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01µF capacitor. When using an external reference, connect REFADJ to V
DD
to
disable the internal bandgap reference.
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Active-Low Chip Select. When CS is high, digital outputs (D11–D0) are high
impedance.
PIN
MAX1267MAX1265
NAME FUNCTION