Datasheet

MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
______________________________________________________________________________________ 15
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0
CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
SSTRB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONTROL BYTE 2S
1
8115 1581
CS
SCLK
DIN
DOUT
S
18 16
18 16
CONTROL BYTE 0
CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
CONVERSION RESULT 1
• • •
• • •
• • •
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Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing
The fastest the MAX1246/MAX1247 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 10a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a µC can drive the
MAX1246/MAX1247. Figure 10b shows the serial-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB
SCLK
DOUT
t
CSS
t
DO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 9. Internal Clock Mode SSTRB Detailed Timing