Datasheet

MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
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Internal Clock
In internal clock mode, the MAX1246/MAX1247 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1246/MAX1247 and three-states DOUT, but it
does not adversely affect an internal clock mode
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
t
CSH
t
CSS
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
CSH
Figure 6. Detailed Serial-Interface Timing
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 16 20 24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1 PD0
B11
MSB
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B0
LSB
ACQUISITION
(f
SCLK
= 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
t
ACQ
A/D STATE
RB1
RB2
RB3
1.5µs
Figure 5. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f
SCLK
≤ 2MHz)