Datasheet

MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
______________________________________________________________________________________ 19
Lowest Power at Higher Throughputs
Figure 13b shows the power consumption with
external-reference compensation in fast power-down,
with one and four channels converted. The external
4.7µF compensation requires a 200µs wait after
power-up with one dummy conversion. This circuit
combines fast multi-channel conversion with the lowest
power consumption possible. Full power-down mode
may provide increased power savings in applications
where the MAX1246/MAX1247 are inactive for long
periods of time, but where intermittent bursts of
high-speed conversions are required.
Internal and External References
The MAX1246 can be used with an internal or external
reference voltage, whereas an external reference is
required for the MAX1247. An external reference can
be connected directly at VREF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at
VREF for both the MAX1246 and the MAX1247. The
MAX1246’s internally trimmed 1.21V reference is buf-
fered with a 2.06 gain. The MAX1247’s REFADJ pin is
also buffered with a 2.00 gain to scale an external 1.25V
reference at REFADJ to 2.5V at VREF.
Internal Reference (MAX1246)
The MAX1246’s full-scale range with the internal refer-
ence is 2.5V with unipolar inputs and ±1.25V with bipo-
lar inputs. The internal reference voltage is adjustable
to ±1.5% with the circuit in Figure 15.
External Reference
With both the MAX1246 and MAX1247, an external ref-
erence can be placed at either the input (REFADJ) or
the output (VREF) of the internal reference-buffer ampli-
fier. The REFADJ input impedance is typically 20kΩ for
the MAX1246, and higher than 100kΩ for the MAX1247.
100
DIN
REFADJ
VREF
1.21V
0V
2.50V
0V
101 1 11100 101
FULLPD FASTPD NOPD FULLPD FASTPD
9ms WAIT
COMPLETE CONVERSION SEQUENCE
t
BUFFEN
≈ 200µs
τ = RC = 20kΩ x C
REFADJ
(ZEROS)
CH1 CH7
(ZEROS)
Figure 14. MAX1246 FULLPD/FASTPD Power-Up Sequence
+3.3V
510k
24k
100k
0.047µF
9
REFADJ
MAX1246
Figure 15. MAX1246 Reference-Adjust Circuit
PD1 PD0 DEVICE MODE
0 0 Full Power-Down
0 1 Fast Power-Down
1 0 Internal Clock
1 1 External Clock
Table 5. Software Power-Down
and Clock Mode
Table 6. Hard-Wired Power-Down
and Internal Clock Frequency
SHDN
STATE
DEVICE
MODE
REFERENCE
BUFFER
COMPENSATION
INTERNAL
CLOCK
FREQUENCY
1 Enabled Internal 225kHz
Floating Enabled External 1.8MHz
0 Power-Down N/A N/A