Datasheet

MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________ 7
NAME FUNCTION
1–8 CH0–CH7 Sampling Analog Inputs
9 COM
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
PIN
10
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1245 down to 10µA (max) supply current; oth-
erwise, the MAX1245 is fully operational. Letting SHDN be open sets the internal clock frequency to 1.5MHz.
Pulling SHDN high sets the internal clock frequency to 225kHz. See
Hardware Power-Down section.
11 VREF External Reference Voltage Input for analog-to-digital conversion
15 DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
14 DGND Digital Ground
13 AGND Analog Ground
12, 20 V
DD
Positive Supply Voltage
19 SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
18
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.
16 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D con-
version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when CS is high (external clock mode).
______________________________________________________________Pin Description
V
DD
6k
DGND
DOUT
C
LOAD
50pF
C
LOAD
50pF
DGND
6k
DOUT
a) High-Z to V
OH
and V
OL
to V
OH
b) High-Z to V
OL
and V
OH
to V
OL
V
DD
6k
DGND
DOUT
C
LOAD
50pF
C
LOAD
50pF
DGND
6k
DOUT
a) V
OH
to High-Z b) V
OL
to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time