Datasheet

selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provid-
ed that the minimum acquisition time, t
ACQ
, is kept
above 2.0µs.
Data Framing
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V
DD
is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated,
and a new one is started.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 13
SSTRB
CS
SCLK
DIN
DOUT
14 8
12
18
20
24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1 PD0
B11
MSB
B10 B9 B2 B1
B0
LSB
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = OPEN)
2 3 5 6 7 9 10 11 19 21 22 23
t
CONV
ACQUISITION
(SCLK = 1.5MHz)
IDLE
A/D STATE
2.0µs
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB • • •
SCLK • • •
DOUT • • •
t
CSS
t
DO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS • • •
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing