Datasheet

MAX1232
Pin Description
Microprocessor Monitor
_______________________________________________________________________________________ 3
Note 1: PBRST is internally pulled up to V
CC
with an internal impedance of typically 40kΩ.
Note 2: Measured with outputs open.
Note 3: All voltages referenced to GND.
Note 4: Guaranteed by desing.
Note 5: PBRST must be held low for a minimum of 20ms to guarantee a reset.
Note 6: t
R
= 5µs.
AC Electrical Characteristics
(V
CC
= +5V ±10%, T
A
= T
MIN
to T
MAX
)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PBRST (Note 5) t
PB
Figure 3 20 ms
PBRST Delay t
PBD
Figure 3 1 4 20 ms
Reset Active Time t
RST
250 610 1000 ms
ST Pulse Width t
ST
Figure 4 75 ns
Figure 4, TD pin = 0V 62.5 150 250
TD pin = open 250 600 1000
ST Timeout Period t
TD
TD pin = V
CC
500 1200 2000
ms
V
CC
Fall Time (Note 4) t
F
Figure 5 10 µs
V
CC
Rise Time (Note 4) t
B
Figure 6 0 µs
V
CC
Detect to RST High and RST
Low
t
BPD
Figure 7, V
CC
falling 100 ns
V
CC
Detect to RST Low and RST
Open (Note 6)
t
BPU
Figure 8, V
CC
rising 250 610 1000 ms
PIN
WIDE SO DIP/SO
NAME FUNCTION
1, 3, 5, 7, 10,
12, 14, 16
—N.C. No Connection
21PBRST
Pushbutton Reset Input. A debounced active-low input that ignores pulses less than 1ms
in duration and is guaranteed to recognize inputs of 20ms or greater.
42TD
Time Delay Set. The watchdog timebase select input (t
TD
= 150ms for TD = 0V, t
TD
=
600ms for TD = open, t
TD
= 1.2s for TD = V
CC
).
63TOL Tolerance Input. Connect to GND for 5% tolerance or to V
CC
for 10% tolerance.
84GND Ground
95RST
Reset Output (Active High). Goes active:
(1) If VCC falls below the selected reset voltage threshold
(2) If PBRST is forced low
(3) If ST is not strobed within the minimum timeout period
(4) During power-up
11 6 RST Reset Output (Active Low, Open-Drain). See RST.
13 7 ST Strobe Input. Input for watchdog timer.
15 8 V
CC
The +5V Power-Supply Input