Datasheet

(V
DD
= 5V, V
SS
= -12V or -15V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 5)
Note 1: These tests are performed at V
DD
= +5V. V
SS
= -15V. Operation over supply is guaranteed by supply-rejection tests.
Note 2: Ideal full-scale transition is at +5V - 3/2 LSB = +4.9991V adjusted for offset error.
Note 3: Guaranteed, not tested.
Note 4: Temperature drift is defined as the change in output voltage from +25°C to T
MIN
or T
MAX
. It is calculated as
T
C
= (ΔV
REF
/V
REF
)/ΔT.
Note 5: Control inputs specified with t
r
= t
f
= 5ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. Output delays are
measured to +0.8V if going low, or +2.4V if going high. For a data-hold time, a change of 0.5V is measured. See Figures 4
and 5 for load circuits.
Note 6: Guaranteed, not tested.
PARAMETER SYMBOL CONDITIONS
T
A
= +25°C MAX121C/E MAX121M
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CONVST Pulse
Width (Note 6)
t
CW
20 30 35 ns
Data-Access Time t
DA
C
L
= 50pF 25 50 65 80 ns
Data-Hold Time t
DH
25 50 65 80 ns
CLKIN to SCLK t
CD
C
L
= 50pF 40 65 85 105 ns
SCLK to SDATA
Skew
t
SC
C
L
= 50pF ±65 ±80 ±100 ns
SCLK to SFRM or
FSTRT Skew
t
SC
C
L
= 50pF ±25 ±35 ±40 ns
Acquisition Time
(Note 6)
t
AQ
400 400 400 ns
Aperture Delay t
AP
10 ns
Aperture Jitter 30 ns
Clock Setup/Hold
Time
t
CK
10 50 10 50 10 50 ns
MAX121 308ksps ADC with DSP Interface and 78dB SINAD
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Timing Characteristics