Datasheet

TMS320 Simple Serial Interface
Figure 22 shows an application circuit using the simplest
interface between the MAX121 and the TMS320. The tim-
ing diagram for this circuit is shown in Figure 23.
In this circuit, the CLKR port of the TMS320 is configured
as a clock output and drives the CLKIN of the MAX121.
The MAX121 output changes state on the rising edge of
the CLKIN while the data is latched into the DR port of
the TMS320 on the falling edge. The XF1 I/O port of the
TMS320 drives the MAX121 CONVST input low to initiate
a conversion. The FSTRT output of the MAX121 drives the
FSR input of the TMS320 to frame the data. A falling edge
on the FSTRT output indicates that the MSB is ready to be
latched. On the next falling clock edge, the MSB is latched
into the TMS320. For this interface, the TMS320 is config-
ured to receive a 16-bit word (RLEN = 01 in the TMS320
serial-port global control register) so the 14 bits of data are
clocked into the DSP, followed by two trailing zeros. At T
A
= +25°C, the clock frequency is limited to approximately
3.2MHz with this interface, due to the CLKIN-to-SDATA
maximum delay of 130ns and the 25ns setup and hold
time requirement for the TMS320.
Figure 24 is a listing of a short program written in the
TMS320 assembly language that initiates conversions in
the TMS320 and ships the output data back to the host
PC. The C language program listed in Figure 25 displays
the results of every 30,000th conversion on the PC
screen, along with the min and max values for all conver-
sions performed during one operating sequence.
Digital Bus/Clock Noise
If the clock is active when the T/H is sampling the input
signal, errors can be caused by coupling from the CLKIN
pin to the analog input. If this is a problem, the clock
should be disabled for one clock cycle while the T/H is
placed into hold mode. In mode 1, the clock should be
disabled (CLKIN = DGND) for one cycle while CONVST
is pulsed low. In mode 2, the clock should be disabled
(CLKIN = DGND) for one clock cycle while CS is driven
low. The clock should be reactivated on the first cycle after
the conversion is started (CONVST or CS pulsed low).
Layout, Grounding and Bypassing
For best system performance, use PCBs with separate
analog and digital ground planes. Wire wrap boards are
not recommended. The two ground planes should be tied
together at the low-impedance power-supply source, as
shown in Figure 26.
Figure 21. TMS320 High-Speed Serial-Interface Timing Diagram
Figure 20. TMS320 High-Speed Serial-lnterface Circuit
CLKIN
t
SU
(FSR)
t
H
(FSR)
CONVST
SCLK
LSBMSB
1 2 14 15
1 2 14 15
D12 D1
SDATA
FSTRT
XF
CONVST
TMS320
MAX121
CLKR SCLK
DR
FSR
SDATA
FSTRT
CLKIN
OSC
CS
INVFRM
INVCLK
DGND
+5V
0.1MHz ≤ F ≤ 5.5MHz
MAX121 308ksps ADC with DSP Interface and 78dB SINAD
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