Datasheet

NEC µPD77230 Serial Interface
Figure 18 shows the connections required to interface the
MAX121 to NEC’s µPD77230 DSP without external glue
logic. The timing diagram is shown in Figure 19. See the
Maximum Clock Rate for Serial Interface section to deter-
mine the maximum usable clock rate for this interface,
substituting t
SISS
for t
SU
in the equations. The t
HSSI
term
in the timing diagram is the minimum data-hold time for
the µPD77230’s serial data input.
An I/O port of the µPD77230 drives the MAX121 CONVST
pin low to initiate a conversion. The MAX121 SFRM out-
put drives the SIEN (Serial Input Enable) terminal of the
DSP low to frame the data. On the next falling edge of
SCLK, the MSB is shifted into the SI (Serial Input) pin of
the µPD77230. SDATA drives the SI terminal of the DSP.
The MSB is followed by the other 13 data bits and two
trailing zeros, after which the SFRM output returns high
to disable the DSP serial input until the next conversion
is initiated.
TMS320 High-Speed Serial Interface
The flexibility of the MAX121 permits the implementa-
tion of a variety of interfaces with the Texas Instruments’
TMS320 DSP. The TMS320 Simple Serial Interface sec-
tion of this data sheet discusses the simplest type of
MAX121-to-TMS320 interface, which works with serial
clock rates up to 3.2MHz.
This section describes an interface that allows the
maximum throughput to be obtained from the MAX121-
to-TMS320 system, by operating the MAX121 at its
maximum clock. Figure 20 shows the interconnections
required to implement this interface. Figure 21 is the tim-
ing diagram for this interface.
The MAX121 CLKIN is driven by an external clock
oscillator. The XFO I/O port of the TMS320 drives the
MAX121 CONVST input low to initiate a conversion.
CLKR (Receive Clock) of the TMS320 is configured as an
input and driven by the MAX121 SCLK output. Data on
the MAX121 SDATA output changes state on the rising
edge of the clock, while data is latched into the DR input
of the TMS320 on the falling edge. This provides one half
clock cycle to meet the setup and hold time requirements
of the TMS320 DR input. The maximum skew between
the MAX121 SCLK and SDATA is ±65ns at +25°C, so one
half clock cycle is more than sufficient to guarantee that
the setup and hold time requirement is satisfied.
The FSTRT output of the MAX121 drives the FSR input
of the TMS320 to frame the data. A falling edge on the
FSTRT output indicates that the MSB is ready to be
latched. On the next falling clock edge, the MSB is latched
into the TMS320. For this interface, the TMS320 is config-
ured to receive a 16-bit word (RLEN = 01 in the TMS320
serial-port global control register) so the 14 bits of data
are clocked into the DSP, followed by two trailing zeros.
Figure 19. NEC µPD77230 Interface Timing Diagram
CLKIN
1 2 14 15 16 17
t
SISS
t
HSS
CONVST
1 2 14 15 16 17
SCLK
(INVCLK = V
DD
)
LSBMSB D12 D1
SFRM
(INVFRM = GND)
SDATA
MAX121 308ksps ADC with DSP Interface and 78dB SINAD
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