Datasheet

Motorola QSPI Serial Interlace
(CPOL = 0, CPHA = 1)
Figure 14 shows the connections required to implement a
QSPI interface with the MAX121. The timing diagram for
this interface is shown in Figure 15. The QSPI standard
is similiar to SPI, with the primary differences as follows:
1) QSPI allows arbitrary length data transfers from 8
to 16 bits, so only one read operation is required to
receive the 14 bits of output data from the MAX121.
2) QSPI allows clock rates up to 4MHz, compared to
2MHz with SPI.
ADSP2101 Serial Interlace
Figure 16 shows the connections required to interface the
MAX121 to Analog Devices’ ADSP2101 DSP. Figure 17
is a plot of the timing diagram. The ADSP2101 has a high-
speed serial interface with a minimum serial data setup
time of 10ns (t
SCS
) and a minimum data-hold time of 10ns
(t
SCH
). This interface permits operation of the MAX121 at
its maximum clock rate of 5.5MHz.
An output port of the ADSP2101 drives the MAX121
CONVST input low to initiate a conversion. The SFRM
output of the MAX121 drives the RFS (Receive Frame
Synchronization) input to the DSP low to indicate that the
MSB has been shifted out of the MAX121 SDATA pin. On
the next falling edge on SCLK, the MSB is shifted into the
ADSP2101 serial input. Note that the MAX121 INVFRM
input is grounded to provide the proper phase for the
SFRM output.
The SCLK terminal of the ADSP2101 is configured as an
input and is driven by the MAX121 SCLK output to clock
data into the DSP. The SFRM output remains low for 16
clock cycles, allowing the 14 data bits to be shifted into
the ADSP2101, followed by 2 trailing zeros.
Figure 12. SPI Interface Timing Diagram
Figure 15. QSPI Interface Timing Diagram
Figure 13. SPI Interface Circuit Figure 14. QSPI Interface Circuit
CLKIN
1ST BYTE READ
1 2
MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
3 4 5 6 7 8 1 2 3 4 5 6 7 8
2ND BYTE READ
CONVST
SDATA
LEADING
ZERO
TRAILING
ZERO
CLKIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
CONVST
SDATA
TRAILING
ZERO
LEADING
ZERO
SS
I/O CONVST
CPOL = 0
CPHA = 1
PROCESSOR
MAX121
SCK
INVFRM
INVCLK
CLKIN
+5V
MISO SDATA
CS
DGND
SS
I/O CONVST
CPOL = 0
CPHA = 1
PROCESSOR
MAX121
SCK
INVFRM
INVCLK
CLKIN
+5V
MISO SDATA
CS
DGND
MAX121 308ksps ADC with DSP Interface and 78dB SINAD
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