Datasheet
(V
DD
= 5V ±5%; V
L
= 2.7V to 3.6V; V
SS
= 0V; f
SCLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
REF
= 4.096V applied to REF pin; T
A
= +25°C, unless other-
wise noted.)
PIN NAME FUNCTION
1–8 CH0–CH7 Sampling Analog Inputs
9 V
SS
Negative Supply Voltage. Tie V
SS
to -5V ±5% or to GND.
10 SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to V
DD
puts
the reference-buffer amplier in internal compensation mode. Leaving SHDN unconnected puts the
reference-buffer amplier in external compensation mode.
11 REF
Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the
reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external
reference mode, disable the internal buffer by pulling REFADJ to V
DD
.
12 REFADJ Input to the Reference-Buffer Amplier. Tie REFADJ to V
DD
to disable the reference-buffer amplier.
13 GND Ground; IN- Input for Single-Ended Conversions
14 V
L
Supply Voltage for Digital Output Pins. Voltage applied to V
L
determines the positive output swing of
the Digital Outputs (DOUT, SSTRB). 2.7V ≤ V
L
≤ 5.25V.
15 DOUT Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
16 SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
the analog-to-digital conversion, and goes high when the conversion is nished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is
high (external clock mode).
17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18 CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
19 SCLK
Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed (Duty cycle must be 40% to 60% in external clock mode).
20 V
DD
Positive Supply Voltage, +5V ±5%
-1.0
-0.8
-0.6
-0.4
0
INTEGRAL NONLINEARITY
vs. DIGITAL
1.0
0.4
0.6
0.8
MAX1202 toc09
DIGITAL CODE
INL (LSB)
3000
0
-0.2
750 1500 2250
0.2
3750
4500
-120
0
FFT PLOT
20
MAX1202 toc10
FREQUENCY (kHz)
AMPLITUDE (dB)
-20
-40
-60
-80
-100
33.25
0
66.50
V
SS
= -5V
MAX1202/MAX1203 5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Maxim Integrated
│
8
www.maximintegrated.com
Typical Operating Characteristics (continued)
Pin Description