Datasheet

(V
DD
= +5V ±5%, V
L
= 2.7V to 3.6V; V
SS
= 0V or -5V ±5%; f
SCLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
cycle (133ksps); MAX1202—4.7μF capacitor at REF pin; MAX1203—external reference, V
REF
= 4.096V applied to REF pin; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at REF
Internal compensation mode 0
µF
External compensation mode 4.7
Reference-Buffer Gain
MAX1202 1.68
V/V
MAX1203 1.64
REFADJ Input Current
MAX1202 ±50
µA
MAX1203 ±5
POWER REQUIREMENTS
Positive Supply Voltage V
DD
5 ±5% V
Negative Supply Voltage V
SS
0 or 5
±5%
V
Positive Supply Current I
DD
Operating mode 1.5 2.5 mA
Fast power-down (Note 9) 30 70
µA
Full power-down (Note 9) 2 10
Negative Supply Current I
SS
Operating mode and fast power-down 50
µA
Full power-down 10
Logic Supply Voltage V
L
2.70 5.25 V
Logic Supply Current (Notes 6, 10) I
L
V
L
= V
DD
= 5V 10 µA
Positive Supply Rejection (Note 11) PSR
V
DD
= 5V ±5%; external reference, 4.096V;
full-scale input
±0.06 ±0.5 mV
Negative Supply Rejection (Note 11) PSR
V
SS
= -5V ±5%; external reference, 4.096V;
full-scale input
±0.01 ±0.5 mV
Logic Supply Rejection (Note 12) PSR External reference, 4.096V; full-scale input ±0.06 ±0.5 mV
MAX1202/MAX1203 5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
www.maximintegrated.com
Maxim Integrated │ 4
Electrical Characteristics (continued)