Datasheet

MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= OV
DD
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k
resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. +25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Input Hysteresis V
HYST
0.15
V
I
IH
V
IH
= V
DD
= OV
DD
±20
Input Leakage
I
IL
V
IL
= 0
±20
µA
Input Capacitance C
IN
5pF
DIGITAL OUTPUTS (D0A/BD7A/B, A/B)
Output Voltage Low V
OL
I
SINK
= -200µA 0.2 V
Output Voltage High V
OH
I
SOURCE
= 200µA
OV
DD
-
0.2
V
Three-State Leakage Current I
LEAK
OE = OV
DD
±10 µA
Three-State Output Capacitance
C
OUT
OE = OV
DD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range V
DD
2.7 3 3.6 V
Output Supply Voltage Range OV
DD
1.7 3 3.6 V
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels
29 36
Sleep mode 3
mA
Analog Supply Current I
VDD
Shutdown, clock idle, PD = OE = OV
DD
0.1 20 µA
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels (Note 6)
8mA
Sleep mode 3
Output Supply Current I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
310
µA
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels
87 108
Sleep mode 9
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD
0.3 60 µW
Offset, V
DD
±5% ±3
Power-Supply Rejection PSRR
Gain, V
DD
±5% ±3
mV/V
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t
DOA
C
L
= 20pF (Notes 1, 7) 6
8.25
ns
CLK Fall to CHB Output Data
Valid
t
DOB
C
L
= 20pF (Notes 1, 7) 6
8.25
ns
Clock Rise/Fall to A/B Rise/Fall
Time
t
DA/B
6ns
OE Fall to Output Enable Time
t
ENABLE
5ns
OE Rise to Output Disable Time
t
DISABLE
5ns
CLK Pulse Width High t
CH
Clock period: 25ns (Note 7)
12.5
±1.5
ns