Datasheet

MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
______________________________________________________________________________________ 21
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR
dB[max]
= 6.02
dB
× N + 1.76
dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst third-order (or higher)
intermodulation products. The individual input tone lev-
els are at -7dB full scale.
Pin-Compatible Upgrades
(Sampling Speed and Resolution)
Chip Information
TRANSISTOR COUNT: 11,601
PROCESS: CMOS
THD
VVV V
V
log =×
++








+
20
2
2
3
2
4
2
5
2
1
ENOB
SINAD
=






- 1.76
6.02
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLK
Figure 11. T/H Aperture Timing
8-BIT PART 10-BIT PART
SAMPLING SPEED
(Msps)
N/A MAX1185 20
MAX1195 MAX1183 40
MAX1197 MAX1182 60
MAX1198 MAX1180 100
N/A MAX1190 120
MAX1196 MAX1186 40, multiplexed