Datasheet

MAX1184
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to. COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 20MHz, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range V
DD
2.7 3.0 3.6 V
Output Supply Voltage Range OV
DD
1.7 2.5 3.6 V
Operating, f
INA or B
= 7.5MHz at -0.5dBFS 35 50
Sleep mode 2.8
mA
Analog Supply Current I
VDD
Shutdown, clock idle, PD = OE = OV
DD
115µA
Operating, C
L
= 15pF, f
INA or B
= 7.5MHz at
-0.5dBFS
3.8 mA
Sleep mode 100
Output Supply Current I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
210
µA
Operating, f
INA or B
= 7.5MHz at -0.5dBFS 105 150
Sleep mode 8.4
mW
Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD
345µW
Offset ±0.2 mV/V
Power-Supply Rejection Ratio PSRR
Gain ±0.1 %/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid t
DO
Figure 3 (Note 5) 5 8 ns
Output Enable Time t
ENABLE
Figure 4 10 ns
Output Disable Time t
DISABLE
Figure 4 1.5 ns
CLK Pulse Width High t
CH
Figure 3, clock period: 50ns
25 ± 7.5
ns
CLK Pulse Width Low t
CL
Figure 3, clock period: 50ns
25 ± 7.5
ns
Wake up from sleep mode (Note 6) 0.51
Wake-Up Time t
WAKE
Wake up from shutdown (Note 6) 1.5
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk f
INA or B
= 7.5MHz at -0.5dBFS -70 dB
Gain Matching f
INA or B
= 7.5MHz at -0.5dBFS 0.02 ±0.2 dB
Phase Matching f
INA or B
= 7.5MHz at -0.5dBFS 0.25 d eg r ees
Note 1: Equivalent dynamic performance is obtainable over full OV
DD
range with reduced C
L
.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.