Datasheet

Detailed Description
The MAX1184 uses a 9-stage, fully-differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages, where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
MAX1184
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 11
V
INA
= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
V
INB
= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
T/H
V
OUT
x2
Σ
FLASH
ADC
DAC
1.5 BITS
10
V
INB
V
IN
STAGE 1 STAGE 2
D9B–D0B
DIGITAL CORRECTION LOGIC
STAGE 8 STAGE 9
2-BIT FLASH
ADC
T/H
T/H
V
OUT
x2
Σ
FLASH
ADC
DAC
1.5 BITS
10
V
INB
STAGE 1 STAGE 2
D9B–D0B
DIGITAL CORRECTION LOGIC
STAGE 8 STAGE 9
2-BIT FLASH
ADC
T/H
Figure 1. Pipelined Architecture—Stage Blocks