Datasheet

Detailed Description
Converter Operation
The MAX1178/MAX1188 use a successive-approxima-
tion (SAR) conversion technique with an inherent track-
and-hold (T/H) stage to convert an analog input into a
16-bit digital output. Parallel outputs provide a high-
speed interface to microprocessors (µPs). The Func-
tional Diagram shows a simplified internal architecture of
the MAX1178/MAX1188. Figure 3 shows a typical oper-
ating circuit for the MAX1178/MAX1188.
Analog Input
Input Scaler
The MAX1178/MAX1188 have an input scaler, which
allows conversion of true bipolar input voltages and
input voltages greater than the power supply, while
operating from a single +5V analog supply. The input
scaler attenuates and shifts the analog input to match
the input range of the internal digital-to-analog converter
(DAC). The MAX1178 input voltage range is ±5V, while
the MAX1188 input voltage range is ±10V. Figure 4
shows the equivalent input circuit of the MAX1178/
MAX1188. This circuit limits the current going into or
out of AIN to less than 1.8mA.
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (Figure 4). In hold mode, the T/H switch-
es open and the capacitive DAC samples the analog
input. During the acquisition, the analog input (AIN)
charges capacitor C
HOLD
. The acquisition ends on the
second falling edge of CS. At this instant, the T/H
switches open. The retained charge on C
HOLD
repre-
sents a sample of the input. In hold mode, the capaci-
tive DAC adjusts during the remainder of the conversion
time to restore node T/H OUT to zero within the limits of
16-bit resolution. Force CS low to put valid data on the
bus after conversion is complete.
MAX1178/MAX1188
16-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
_______________________________________________________________________________________ 7
Pin Description (continued)
PIN NAME FUNCTION
13 HBEN
High-Byte Enable Input. Used to multiplex the 16-bit conversion result.
1: MSB available on the data bus.
0: LSB available on the data bus.
14 CS
Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C
is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result
onto the bus when R/C is high.
15 DGND Digital Ground
16 DV
DD
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
17 D0/D8 Tri-State Digital-Data Output. D0 is the LSB.
18 D1/D9 Tri-State Digital-Data Output
19 D2/D10 Tri-State Digital-Data Output
20 D3/D11 Tri-State Digital-Data Output
DGND
1mA
C
LOAD
= 20pF
DO–D15
DO–D15
C
LOAD
= 20pF
1mA
DGND
DV
DD
a) HIGH-Z TO V
OH
,
V
OL
TO V
OH
, AND
V
OH
TO HIGH-Z
b) HIGH-Z TO V
OL
,
V
OH
TO V
OL
, AND
V
OL
TO HIGH-Z
Figure 1. Load Circuits