Datasheet

MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
6 _______________________________________________________________________________________
Note 9: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 10: C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3

V
DV
DD
and 0.7

V
DV
DD
.
Note 11: f
SCL
must meet the minimum clock low time plus the rise/fall times.
ELECTRICAL CHARACTERISTICS (continued)
(V
AV
DD
= +4.75V to +5.25V, V
DV
DD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external
reference applied to REF, REFADJ = AVDD, C
REF
= 10μF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
Figure 1. I
2
C Serial Interface Timing
t
HD,STA
t
HD,STA
t
HIGH
t
HIGH
t
R
t
RCL
t
F
t
FCL
t
HD,STA
S Sr A
SCL
SDA
t
SU,STA
t
SU,STO
t
SU,STO
t
RCL1
t
R
t
F
t
BUF
t
BUF
t
LOW
t
SU,DAT
t
HD,DAT
t
HD,DAT
PS
t
SU,DAT
t
HD,STA
S Sr A
SCL
SDA
t
SU,STA
t
LOW
P
S
HS-MODE
F/S-MODE
A. F/S-MODE I
2
C SERIAL INTERFACE TIMING
B. HS-MODE I
2
C SERIAL INTERFACE TIMING
t
RDA
t
FDA
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 2. Load Circuit
V
OUT
V
DD
I
OL
= 3mA
I
OH
= 0mA
400pF
DIGITAL
I/O