Datasheet
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
_______________________________________________________________________________________ 5
Note 1: DC accuracy is tested at V
AV
DD
= +5.0V and V
DV
DD
= +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nullified.
Note 4: One sample is achieved every 18 clocks in continuous conversion mode:
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
Note 7: ADC performance is limited by the converter’s noise floor, typically 225μV
P-P
.
Note 8:
PSRR
V (5.25V)-V (4.75V)
2
V
5.25V
FS FS
N
REF
=
⎡
⎣
⎤
⎦
×
-- 4.75V
where N is the number of bits ( ).16
t2
1
f
ACQ
SCL
=×
⎛
⎝
⎜
⎞
⎠
⎟
f
1 clocks
f
t
SAMPLE
SCL
C
-1
=+
⎛
⎝
⎜
⎞
⎠
⎟
8
ONV
ELECTRICAL CHARACTERISTICS (continued)
(V
AV
DD
= +4.75V to +5.25V, V
DV
DD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external
reference applied to REF, REFADJ = AVDD, C
REF
= 10μF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency f
SCLH
(Note 11) 1.7 MHz
Hold Time (Repeated) Start
Condition
t
HD, STA
160 ns
Low Period of the SCL Clock t
LOW
320 ns
High Period of the SCL Clock t
HIGH
120 ns
Setup Time for a Repeated
START Condition
t
SU, STA
160 ns
Data Hold Time t
HD, DAT
(Note 9) 0 150 ns
Data Setup Time t
SU, DAT
10 ns
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
(Note 10) 10 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
t
RCL1
(Note 10) 20 160 ns
Fall Time of SCL Signal
t
FCL
(Note 10) 20 80 ns
Rise Time of SDA Signal
t
RDA
(Note 10) 20 160 ns
Fall Time of SDA Signal
t
FDA
(Note 10) 20 160 ns
Setup Time for STOP Condition t
SU, STO
160 ns
Capacitive Load for Each Bus
C
B
400 pF
Pulse Width of Spike Suppressed t
SP
10 ns