Datasheet

MAX1169
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, lengthen the
acquisition time by reducing f
SCL
. The MAX1169 pro-
vides two SCL cycles (t
ACQ
) in which the track-and-
hold capacitance must acquire a charge representing
the input signal. Minimize the input source impedance
(R
SOURCE
) to allow the track-and-hold capacitance to
charge within the allotted time. R
SOURCE
should be
less than 11.3kΩ for f
SCL
= 400kHz and less than 2kΩ
for f
SCL
= 1.7MHz. R
SOURCE
is calculated with the fol-
lowing equation:
R
fIn
(
22
)
C
R
SOURCE
SCL
N
IN
IN
≤
×××
−
2
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
12 ______________________________________________________________________________________
Figure 3. MAX1169 Simplified Functional Diagram
AIN
AGNDS
CONTROL
LOGIC
4MHz
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
T/H
SAR
ADC
REF
CLOCK
IN
OUT
+4.096V
REFERENCE
REFADJ
REF
5kΩ
ADD0
ADD1
ADD2
ADD3
DVDD
AVDD
DGND
SCL
SDA
AGND
8
13
12
11
9
1
2
3
4
5
6
7
10
14
MAX1169
A
V
= 1.0
Figure 4. Typical Application Circuit
AIN
REF
10μF
0.1μF
REFADJ
AGNDS
AVDD
0.1μF
AGND DGND
ANALOG
SOURCE
ADD1
ADD0
ADD2
SCL
SDA
DVDD
0.1μF
3.0V
5.0V
μC
V
DD
SDA
SCL
R
P
R
P
ADD3
V
SS
8
13
12
11
14
91
2
3
4
5
6
7
10
I
2
C ADDRESS IS 0110111.
MAX1169