Datasheet

8 ______________________________________________________________________________________
MAX11661–MAX11666
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11664) (continued)
(V
DD
= 2.2V to 3.6V, V
REF
= V
DD
, V
OVDD
= V
DD
, f
SCLK
= 8MHz, 50% duty cycle, 500ksps; C
DOUT
= 10pF, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 1)
ELECTRICAL CHARACTERISTICS (MAX11663)
(V
DD
= 2.2V to 3.6V. f
SCLK
= 8MHz, 50% duty cycle, 500ksps. C
DOUT
= 10pF, T
A
= -40NC to +125NC, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Positive Supply Voltage V
DD
2.2 3.6 V
Digital I/O Supply Voltage V
OVDD
1.5 V
DD
V
Positive Supply Current
(Full-Power Mode)
I
VDD
V
AIN_
= V
GND
1.67
mA
I
OVDD
V
AIN_
= V
GND
0.1
Positive Supply Current
(Full-Power Mode), No Clock
I
VDD
1.5 mA
Power-Down Current I
PD
Leakage only 1.3 10
FA
Line Rejection V
DD
= 2.2V to 3.6V, V
REF
= 2.2V 0.17 LSB/V
TIMING CHARACTERISTICS (Note 2)
Quiet Time t
Q
(Note 3) 4 ns
CS Pulse Width
t
1
(Note 3) 10 ns
CS Fall to SCLK Setup
t
2
(Note 3) 5 ns
CS Falling Until DOUT High-
Impedance Disabled
t
3
(Note 3) 1 ns
Data Access Time After SCLK
Falling Edge (Figure 2)
t
4
V
OVDD
= 2.2V to 3.6V 15
ns
V
OVDD
= 1.5V to 2.2V 16.5
SCLK Pulse Width Low t
5
Percentage of clock period (Note 3) 40 60 %
SCLK Pulse Width High t
6
Percentage of clock period (Note 3) 40 60 %
Data Hold Time From SCLK
Falling Edge
t
7
Figure 3 5 ns
SCLK Falling Until DOUT High
Impedance
t
8
Figure 4 (Note 3) 2.5 14 ns
Power-Up Time Conversion cycle (Note 3) 1 Cycle
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL
Q0.5
LSB
Differential Nonlinearity DNL No missing codes
Q0.5
LSB
Offset Error OE
Q0.3 Q1.3
LSB
Gain Error GE Excluding offset and reference errors
Q0.15 Q1.3
LSB
Total Unadjusted Error TUE
Q1
LSB