Datasheet

______________________________________________________________________________________ 15
MAX11661–MAX11666
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices
Figure 2. Setup Time After SCLK Falling Edge
Figure 3. Hold Time After SCLK Falling Edge
Figure 4. SCLK Falling Edge DOUT Three-State
123
4567 8910 11 12 13 14 15 16
16
1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
SCLK
HIGH
IMPEDANCE
t
6
t
2
t
5
t
1
0
SAMPLE
SAMPLE
00
(MSB)
t
3
t
4
t
7
t
8
t
QUIET
t
CONVERT
1/f
SAMPLE
t
ACQ
CS
HIGH
IMPEDANCE
V
IH
V
IL
NEW DATAOLD DATADOUT
SCLK
t
4
V
IH
V
IL
OLD DATA NEW DATA
DOUT
SCLK
t
7
HIGH IMPEDANCE
DOUT
SCLK
t
8