Datasheet

Note 1: All WLP devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2: For DC accuracy, the MAX11646 is tested at V
DD
= 5V and the MAX11647 is tested at V
DD
= 3V, with an external refer-
ence for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a 0.1µF capaci-
tor and a 2kΩ series resistor (see the
Typical Operating Circuit ).
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10: Measured as follows for the MAX11647:
and for the MAX11646, where N is the number of bits:
Note 11: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T
A
= +25°C.
Note 13: C
B
= total capacitance of one bus line in pF.
Note 14: f
SCL
must meet the minimum clock low time plus the rise/fall times.
V
FS
VV
FS
V
V
REF
V
N
(. ) (. )
(.
55 45
2
55
−
⎡
⎣
⎤
⎦
×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−− 45.)V
VVVV
V
V
FS FS
N
REF
(. ) (. )
(.
36 27
2
36
−
⎡
⎣
⎤
⎦
×
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−− 27.)V
MAX11646/MAX11647
Low-Power, 1-/2-Channel, I
2
C, 10-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.7V to 3.6V (MAX11647), V
DD
= 4.5V to 5.5V (MAX11646), V
REF
= 2.048V (MAX11647), V
REF
= 4.096V (MAX11646),
f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C. See Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
Measured from 0.3V
DD
to 0.7V
DD
20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
t
RCL1
Measured from 0.3V
DD
to 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3V
DD
to 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3V
DD
to 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3V
DD
to 0.7V
DD
(Note 12) 20 160 ns
Setup Time for a STOP (P)
Condition
t
SU
:
STO
160 ns
Capacitive Load for Each Bus
Line
C
B
400 pF
Pulse Width of Spike
t
SP
(Notes 11 and 14) 0 10 ns