Datasheet

MAX11638/MAX11639/MAX11642/MAX11643
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
10 ______________________________________________________________________________________
Pin Description
MAX11638
MAX11639
(8 CHANNELS)
MAX11642
MAX11643
(16 CHANNELS)
NAME FUNCTION
1–7 — AIN0–AIN6 Analog Inputs
— 1–15 AIN0–AIN14 Analog Inputs
8 — CNVST/AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
— 16 CNVST/AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3 for details
on programming the setup register.
9 17 REF Reference Input. Bypass to GND with a 0.1µF capacitor.
10 18 GND Ground
11 19 V
DD
Power Input. Bypass to GND with a 0.1µF capacitor.
12 20 CS
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
13 21 SCLK
Serial Clock Input. Clocks data in and out of the serial interface (duty
cycle must be 40% to 60%). See Table 3 for details on programming the
clock mode.
14 22 DIN
Serial Data Input. DIN data is latched into the serial interface on the
rising edge of SCLK.
15 23 DOUT
Serial Data Output. Data is clocked out on the falling edge of SCLK. High
impedance when CS is connected to V
DD
.
16 24 EOC End of Conversion Output. Data is valid after EOC pulls low.