Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 24

General Description

The MAX11638/MAX11639/MAX11642/MAX11643 are

serial 8-bit analog-to-digital converters (ADCs) with an

internal reference. These devices feature on-chip FIFO,

scan mode, internal clock mode, internal averaging,

and AutoShutdown™. The maximum sampling rate is

300ksps using an external clock. The MAX11642/

MAX11643 have 16 input channels and the MAX11638/

MAX11639 have 8 input channels. These four devices

operate from either a +3V supply or a +5V supply, and

contain a 10MHz SPI-/QSPI™-/MICROWIRE

-compati-

ble serial port.

The MAX11638/MAX11639 are available in 16-pin

QSOP packages. The MAX11642/MAX11643 are avail-

able in 24-pin QSOP packages. All four devices are

specified over the extended -40°C to +85°C tempera-

ture range.

Applications

System Supervision

Data-Acquisition Systems

Industrial Control Systems

Patient Monitoring

Data Logging

Instrumentation

Features

o Analog Multiplexer with Track-and-Hold (T/H)

16 Channels (MAX11642/MAX11643)

8 Channels (MAX11638/MAX11639)

o Single Supply

2.7V to 3.6V (MAX11639/MAX11643)

4.75V to 5.25V (MAX11638/MAX11642)

o Internal Reference

2.5V (MAX11639/MAX11643)

4.096V (MAX11638/MAX11642)

o External Reference: 1V to V

o 16-Entry First-In/First-Out (FIFO)

o Scan Mode, Internal Averaging, and Internal Clock

o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing

Codes Over Temperature

o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible

Interface

o Small Packages

16-Pin QSOP (MAX11638/MAX11639)

24-Pin QSOP (MAX11642/MAX11643)

MAX11638/MAX11639/MAX11642/MAX11643

8-Bit, 16-/8-Channel, 300ksps ADCs

with FIFO and Internal Reference

________________________________________________________________

Maxim Integrated Products

AIN0

TOP VIEW

EOC

DOUT

DIN

SCLK

GND

REF

MAX11638

MAX11639

QSOP

AIN1

AIN2

AIN5

AIN3

AIN4

AIN6

CNVST/AIN7

Pin Configurations

19-6035; Rev 0; 9/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART

NUMBER

INPUTS

SUPPLY

VOLTAGE

RANGE (V)

PACKAGE

MAX11638EEE+T 8 4.75 to 5.25 16 QSOP

MAX11639EEE+T 8 2.7 to 3.6 16 QSOP

MAX11642EEG+T 16 4.75 to 5.25 24 QSOP

MAX11643EEG+T 16 2.7 to 3.6 24 QSOP

Pin Configurations continued at end of data sheet.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

Note: All devices are specified over the -40°C to +85°C operating

temperature range.

Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

Summary of content (22 pages)

PAGE 1
9-6035; Rev 0; 9/11 KIT ATION EVALU E L B AVAILA 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Features The MAX11638/MAX11639/MAX11642/MAX11643 are serial 8-bit analog-to-digital converters (ADCs) with an internal reference. These devices feature on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum sampling rate is 300ksps using an external clock.
PAGE 2
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V) AIN0–AIN13, CNVST/AIN_, REF to GND ...........................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................
PAGE 3
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference (VDD = +2.7V to +3.6V (MAX11639/MAX11643), VDD = +4.75V to +5.25V (MAX11638/MAX11642), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock 50% duty cycle), VREF = 2.5V (MAX11639/MAX11643), VREF = 4.096V (MAX11638/MAX11642), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V (MAX11639/MAX11643), VDD = +4.75V to +5.25V (MAX11638/MAX11642), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock 50% duty cycle), VREF = 2.5V (MAX11639/MAX11643), VREF = 4.096V (MAX11638/MAX11642), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference (VDD = +2.7V to +3.6V (MAX11639/MAX11643), VDD = +4.75V to +5.25V (MAX11638/MAX11642), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock 50% duty cycle), VREF = 2.5V (MAX11639/MAX11643), VREF = 4.096V (MAX11638/MAX11642), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (continued) (VDD = 3V and VREF = 2.5V (MAX11639/MAX11643), VDD = 5V and VREF = 4.096V (MAX11638/MAX11642), fSCLK = 4.8MHz, CLOAD = 30pF, fSAMPLE = 300ksps, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE SINAD vs. FREQUENCY 51.5 51.0 0 75 MAX11639/MAX11643 MAX11638/MAX11642 50.5 SFDR (dB) SINAD (dB) 0.1 50.0 49.5 -0.1 49.0 -0.2 48.0 MAX11638 toc06 80 MAX11638 toc05 MAX11639/MAX11643 SFDR vs. FREQUENCY 52.
PAGE 7
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference MAX11639/MAX11643 0.4 0.6 1200 1000 0.5 IDD (µA) EXTERNAL REFERENCE 0.4 800 0.2 400 0.3 0.2 0.3 600 MAX11638 toc13 0.7 1400 0.1 0.1 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 MAX11638/MAX11642 0 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 VDD (V) VDD (V) MAX11639/MAX11643 0 SUPPLY CURRENT vs. TEMPERATURE MAX11638 toc14 INTERNAL REFERENCE 2200 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3V and VREF = 2.5V (MAX11639/MAX11643), VDD = 5V and VREF = 4.096V (MAX11638/MAX11642), fSCLK = 4.8MHz, CLOAD = 30pF, fSAMPLE = 300ksps, TA = +25°C, unless otherwise noted.) 2.502 MAX11638 toc18 4.099 MAX11638/MAX11642 4.098 2.500 4.096 2.499 4.095 2.498 2.497 4.094 4.85 4.95 5.05 5.15 3.0 2.7 5.25 3.6 VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE MAX11638 toc20 4.12 MAX11638/MAX11642 4.
PAGE 9
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference MAX11638/MAX11642 0.2 GAIN ERROR (LSB) 0.7 0.6 -0.1 0.4 10 35 60 -40 85 -15 10 35 60 4.85 4.75 85 4.95 GAIN ERROR vs. SUPPLY VOLTAGE MAX11639/MAX11643 5.15 5.25 GAIN ERROR vs. TEMPERATURE 0.6 MAX11638 toc27 0.20 5.05 VDD (V) TEMPERATURE (°C) TEMPERATURE (°C) MAX11638 toc28 -15 -40 0.1 0 0.5 0 MAX11638 toc26 MAX11639/MAX11643 OFFSET ERROR (LSB) 0.3 MAX11638 toc25 0.8 MAX11638 toc24 0.
PAGE 10
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Pin Description MAX11638 MAX11639 (8 CHANNELS) 10 MAX11642 MAX11643 (16 CHANNELS) NAME FUNCTION 1–7 — AIN0–AIN6 Analog Inputs — 1–15 AIN0–AIN14 Analog Inputs 8 — CNVST/AIN7 Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on programming the setup register. — 16 CNVST/AIN15 Active-Low Conversion Start Input/Analog Input 15.
PAGE 11
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference MAX11638/MAX11639/MAX11642/MAX11643 CS tCP tCH tCSS0 tCSH1 tCL tCSH0 tCSS1 SCLK tDH tDS DIN tDOT tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN0 AIN1 T/H AIN15 8-BIT SAR ADC FIFO AND ACCUMULATOR INTERNAL REFERENCE REF MAX11638/MAX11639/ MAX11642/MAX11643 Figure 2.
PAGE 12
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Converter Operation The MAX11638/MAX11639/MAX11642/MAX11643 ADCs use a successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert voltage signals into an 8-bit digital result. This singleended configuration supports unipolar signal ranges.
PAGE 13
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference where RIN = 1.5kΩ, RS is the source impedance of the input signal, and tPWR = 1µs, the power-up time of the device. The varying power-up times are detailed in the explanation of the clock mode conversions. When the conversion is internally timed, tACQ is never less than 1.4µs, and any source impedance below 300Ω does not significantly affect the ADC’s AC performance.
PAGE 14
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01.
PAGE 15
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference BIT NAME BIT — 7 (MSB) — 6 Set to 1 to select setup register. CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. MAX11638/MAX11639/MAX11642/MAX11643 Table 3. Setup Register* FUNCTION Set to zero to select setup register. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference mode configuration. REFSEL0 2 Reference mode configuration. — 1 Don’t care. — 0 (LSB) Don’t care.
PAGE 16
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT — 7 (MSB) FUNCTION Set to zero to select averaging register. — 6 Set to zero to select averaging register. — 5 Set to 1 to select averaging register. AVGON 4 Set to 1 to turn averaging on. Set to zero to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans.
PAGE 17
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Output Data Format Figures 4–7 illustrate the conversion timing for the MAX11638/MAX11639/MAX11642/MAX11643. The 8-bit conversion result is output in MSB-first format with four leading zeros followed by 10-bit data and four trailing zeros. DIN data is latched into the serial interface on the rising edge of SCLK. Data on DOUT transitions on the falling edge of SCLK. Conversions in clock modes 00 and 01 are initiated by CNVST.
PAGE 18
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference CNVST (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT MSB1 LSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6.
PAGE 19
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference (ACQUISITION1) (ACQUISITION2) (CONVERSION1) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the 8th and 9th cycles, the pulse width must be less than 100µs.
PAGE 20
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL is measured using the end-point method.
PAGE 21
8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Chip Information PROCESS: BiCMOS TOP VIEW + AIN0 1 AIN1 2 23 DOUT AIN2 3 22 DIN AIN3 4 AIN4 5 Package Information 24 EOC 21 SCLK MAX11642 MAX11643 For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 22
MAX11638/MAX11639/MAX11642/MAX11643 8-Bit, 16-/8-Channel, 300ksps ADCs with FIFO and Internal Reference Revision History REVISION NUMBER REVISION DATE 0 9/11 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.