Datasheet

MAX11634–MAX11637
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
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Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX11634–MAX11637. The 12-bit conversion result is
output in MSB-first format with four leading zeros. DIN
data is latched into the serial interface on the rising
edge of SCLK. Data on DOUT transitions on the falling
edge of SCLK. Conversions in clock modes 00 and 01
are initiated by CNVST. Conversions in clock modes 10
and 11 are initiated by writing an input data byte to the
conversion register. Data is binary for unipolar mode and
two’s complement for bipolar mode.
BIT NAME BIT FUNCTION
UCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion
UCH2/3 6 Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion
UCH4/5 5 Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion
UCH6/7 4 Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion
X 3 Don’t care
X 2 Don’t care
X 1 Don’t care
X 0 (LSB) Don’t care
Table 4. Unipolar Mode Register (Addressed Through Setup Register)
BIT NAME BIT FUNCTION
BCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion
BCH2/3 6 Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion
BCH4/5 5 Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion
BCH6/7 4 Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion
X 3 Don’t care
X 2 Don’t care
X 1 Don’t care
X 0 (LSB) Don’t care
Table 5. Bipolar Mode Register (Addressed Through Setup Register)