Datasheet

Note 8: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive.
(V
DD
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
DD
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632),
f
SAMPLE
=300kHz, f
SCLK
= 4.8MHz (50% duty cycle), V
REF
= 2.5V (MAX11627//MAX11629/MAX11633); V
REF
= 4.096V (MAX11626/
MAX11628/MAX11632), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
V
DD
= +5V, V
REF
= +4.096V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.
V
DD
= +3V, V
REF
= +2.5V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
Externally clocked conversion 208
ns
Data I/O 100
SCLK Pulse Width High t
CH
40 ns
SCLK Pulse Width Low t
CL
40 ns
SCLK Fall to DOUT Transition t
DOT
C
LOAD
= 30pF 40 ns
CS Rise to DOUT Disable t
DOD
C
LOAD
= 30pF 40 ns
CS Fall to DOUT Enable t
DOE
C
LOAD
= 30pF 40 ns
DIN to SCLK Rise Setup t
DS
40 ns
SCLK Rise to DIN Hold t
DH
0 ns
CS Low to SCLK Setup t
CSS0
40 ns
CS High to SCLK Setup t
CSS1
40 ns
CS High After SCLK Hold t
CSH1
0 ns
CS Low After SCLK Hold t
CSH0
0 4 µs
CNVST Pulse Width Low
t
CSPW
CKSEL = 00 40 ns
CKSEL = 01 1.4 µs
CS or CNVST Rise to EOC
Low (Note 8)
Voltage conversion 7
µs
Reference power-up 65
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11626 toc02
OUTPUT CODE (DECIMAL)
INL (LSB)
307220481024
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
MAX11627/MAX11629/MAX11633
f
SAMPLE
= 300ksps
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX11626 toc03
OUTPUT CODE (DECIMAL)
DNL (LSB)
307220481024
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
MAX11626/MAX11628/MAX11632
f
SAMPLE
= 300ksps
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11626 toc01
OUTPUT CODE (DECIMAL)
INL (LSB)
307220481024
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
MAX11626/MAX11628/MAX11632
f
SAMPLE
= 300ksps
MAX11626–MAX11629/
MAX11632/MAX11633
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
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Maxim Integrated │ 5
Timing Characteristics (Figure 1)
Typical Operating Characteristics