Datasheet

Power-Up Default State
The MAX11626–MAX11629/MAX11632/MAX11633
power up with all blocks in shutdown, including the refer-
ence. All registers power up in state 00000000, except
for the setup register, which powers up in clock mode 10
(CKSEL1 = 1)
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX11626–MAX11629/MAX11632/MAX11633. The
12-bit conversion result is output in MSB-first format with
four leading zeros. DIN data is latched into the serial
interface on the rising edge of SCLK. Data on DOUT tran-
sitions on the falling edge of SCLK. Conversions in clock
modes 00 and 01 are initiated by CNVST. Conversions
in clock modes 10 and 11 are initiated by writing an input
data byte to the conversion register. Data output is binary.
Internally Timed Acquisitions and
Conversions Using CNVST
Performing Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscillator.
Results are added to the internal FIFO to be read out
later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX11626–MAX11629/
MAX11632/MAX11633 then wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes low
before pulling CS low to communicate with the serial inter-
face. EOC stays low until CS or CNVST is pulled low again.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01 In clock
mode 01, conversions are requested one at a time using
CNVST and performed automatically using the internal
oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for at
least 1.4μs to complete the acquisition. If the internal ref-
erence needs to wake up, an additional 65μs is required
for the internal reference to power up.
Set CNVST high to begin a conversion. After the conver-
sion is complete, the ADC shuts down and pulls EOC low.
EOC stays low until CS or CNVST is pulled low again.
Wait until EOC goes low before pulling CS or CNVST low.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result, as specified by the
averaging register, the scan logic automatically switches
the analog input multiplexer to the next-requested chan-
nel. The result is available on DOUT once EOC has been
pulled low.
Figure 4. Clock Mode 00 Timing
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
DOUT
MSB1
LSB1
MSB2
SCLK
CNVST
EOC
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
MAX11626–MAX11629/
MAX11632/MAX11633
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
www.maximintegrated.com
Maxim Integrated │ 17