Datasheet

Converter Operation
The MAX11626–MAX11629/MAX11632/MAX11633 ADCs
use a successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert volt-
age signals into a 12-bit digital result. This single-ended
configuration supports unipolar signal ranges.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias prefiltering of the
input signals is necessary to avoid high-frequency signals
aliasing into the frequency band of interest.
Analog Input Protection
Internal ESD protection diodes clamp all pins to V
DD
and
GND, allowing the inputs to swing from (GND - 0.3V) to
(V
DD
+ 0.3V) without damage. However, for accurate con-
versions near full scale, the inputs must not exceed V
DD
by more than 50mV or be lower than GND by 50mV. If an
off-channel analog input voltage exceeds the supplies,
limit the input current to 2mA.
3-Wire Serial Interface
The MAX11626–MAX11629/MAX11632/MAX11633 fea-
ture a serial interface compatible with SPI/QSPI and
MICROWIRE devices. For SPI/QSPI, ensure the CPU
serial interface runs in master mode so it generates
the serial clock signal. Select the SCLK frequency of
10MHz or less, and set clock polarity (CPOL) and phase
(CPHA) in the μP control registers to the same value. The
MAX11626–MAX11629/MAX11632/MAX11633 operate
with SCLK idling high or low, and thus operate with CPOL
= CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch
input data at DIN on the rising edge of SCLK. Output data
at DOUT is updated on the falling edge of SCLK. Results
are output in binary format.
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. A high-to-low tran-
sition on CS initiates the data input operation. The input
data byte and the subsequent data bytes are clocked
from DIN into the serial interface on the rising edge of
SCLK. Tables 1–5 detail the register descriptions. Bits 5
and 4, CKSEL1 and CKSEL0, respectively, control the
clock modes in the setup register (see Table 3). Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock mode
00 to configure CNVST/AIN_ to act as a conversion start
and use it to request the programmed, internally timed
conversions without tying up the serial bus. In clock mode
01, use CNVST to request conversions one channel at a
time, controlling the sampling speed without tying up the
serial bus. Request and start internally timed conversions
through the serial interface by writing to the conversion
register in the default clock mode 10. Use clock mode 11
with SCLK up to 4.8MHz for externally timed acquisitions
to achieve sampling rates up to 300ksps. Clock mode 11
disables scanning and averaging. See Figures 4–7 for
timing specifications and how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next input data
byte (for clock modes 00 and 10). In clock mode 01, EOC
goes low after the ADC completes each requested opera-
tion. EOC goes high when CS or CNVST goes low. EOC
is always high in clock mode 11.
Single-Ended Inputs
The single-ended analog input conversion modes can be
configured by writing to the setup register (see Table 3).
Single-ended conversions are internally referenced to GND
(see Figure 3).
AIN0–AIN3 are available on the MAX11626–MAX11629/
MAX11632/MAX11633. AIN4–AIN7 are only available on
the MAX11628–MAX11633. AIN8–AIN15 are only avail-
able on the MAX11632/MAX11633. See Tables 2–5 for
more details on configuring the inputs. For the inputs that
can be configured as CNVST or an analog input, only one
can be used at a time.
Unipolar
The MAX11626–MAX11629/MAX11632/MAX11633
always operate in unipolar mode. The analog inputs are
internally referenced to GND with a full-scale input range
from 0 to V
REF
.
Figure 3. Equivalent Input Circuit
+
-
HOLD
CIN+
REF
GND
DAC
CIN-
V
DD
/2
COMPARATOR
AIN0-AIN15
GND
HOLD
HOLD
MAX11626–MAX11629/
MAX11632/MAX11633
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
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